ELANSC520 datasheet(79/440 Pages) AMD

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PCI Bus Host Bridge Registers

Élan™SC520 Microcontroller Register Set Manual

6-15

PCI Configuration Address (PCICFGADR)

Direct-Mapped

I/O Address 0CF8h

This register is used to specify the information to be driven out during the address phase of the next configuration

cycle, which is initiated by a subsequent read or write of the PCICFGDATA register (see page 6-17).

Bit Definitions

Bit

ENABLE

Reserved

Reset

00000000

R/W

R/W!

RSV

Bit

BUS_NUM[7–0]

Reset

00000000

R/W

R/W!

Bit

DEVICE_NUM[4–0]

FUNCTION_NUM[2–0]

Reset

00000000

R/W

R/W!

Bit

REGISTER_NUM[5–0]

Reserved

Reset

00000000

R/W

R/W!

RSV!

Bit

Name

Function

ENABLE

Enable

0 = Accesses to the PCICFGDATA register (see page 6-17) are not converted to configuration

cycles on the PCI bus. They remain normal I/O cycles.

1 = Accesses to the PCICFGDATA register are converted to configuration cycles on the PCI

bus.

30–24

Reserved

This bit field should be written to 0 for normal system operation.

23–16

BUS_NUM[7–0]

Bus Number

This bit field specifies the PCI bus number to which the configuration cycle is addressed.

00h = Specifies the PCI bus that is connected to the ÉlanSC520 microcontroller’s host bridge.

This causes the host bridge to perform a type zero configuration cycle.

Other values = The host bridge performs a type one configuration cycle. In a type one

configuration cycle, the contents of this bit field (BUS_NUM) are driven unchanged on

the PCI bus during the address phase of the cycle.

If the BUS_NUM and DEVICE_NUM bit fields are both 0, the configuration cycle does not

appear on the PCI bus because this combination addresses the internal PCI-indexed

registers of the host bridge.

ELANSC520 Datasheet(PDF) 79 Page - Advanced Micro Devices

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