ELANSC520 datasheet(77/440 Pages) AMD

77 / 440 page

PCI Bus Host Bridge Registers

Élan™SC520 Microcontroller Register Set Manual

6-13

Programming Notes

This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset

is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3).

5M_RTRTO_

IRQ_STA

Master Retry Time-Out Interrupt Status

This bit is set when the master controller retry time-out counter expires.

0 = Master retry time-out has not occurred.

1 = Master retry time-out has occurred.

This bit is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (M_RTRTO_IRQ_ENB

in the HBMSTIRQCTL register, see page 6-10).

M_TABRT_

IRQ_STA

Master Target Abort Interrupt Status

This bit is set when a master controller transaction is terminated with a target abort.

0 = Master controller transaction has not been terminated with a target abort.

1 = Master controller transaction has been terminated with a target abort.

This bit is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (M_TABRT_IRQ_ENB in

the HBMSTIRQCTL register, see page 6-10).

M_MABRT_

IRQ_STA

Master Abort Interrupt Status

This bit is set when a master controller transaction is terminated with a master abort.

0 = Master controller transaction has not been terminated with a master abort.

1 = Master controller transaction has been terminated with a master abort.

This bit is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (M_MABRT_IRQ_ENB

in the HBMSTIRQCTL register, see page 6-10).

M_SERR_

IRQ_STA

Master System Error Interrupt Status

This bit is set when the master controller detects the system error signal asserted.

0 = Master controller has not detected the system error signal asserted.

1 = Master controller has detected the system error signal asserted.

This bit is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (M_SERR_IRQ_ENB in

the HBMSTIRQCTL register, see page 6-10).

M_RPER_

IRQ_STA

Master Received Parity Error Interrupt Status

This bit is set when the master controller detects the parity error signal asserted during a

master controller write transaction or during the address phase of a master controller read

transaction.

0 = Master controller has not detected the parity error signal asserted.

1 = Master controller has detected the parity error signal asserted.

This bit is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (M_RPER_IRQ_ENB in

the HBMSTIRQCTL register, see page 6-10).

M_DPER_

IRQ_STA

Master Detected Parity Error Interrupt Status

This bit is set when the master controller detects a parity error during a master controller read

transaction.

0 = Master controller has not detected a parity error.

1 = Master controller has detected a parity error.

This bit is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (M_DPER_IRQ_ENB in

the HBMSTIRQCTL register, see page 6-10).

Bit

Name

Function

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