ELANSC520 datasheet(65/440 Pages) AMD

65 / 440 page

Élan™SC520 Microcontroller Register Set Manual

6-1

CHAPTER

6 PCI BUS HOST BRIDGE REGISTERS

6.1

OVERVIEW

This chapter describes the PCI bus host bridge controller registers of the ÉlanSC520

microcontroller.

The ÉlanSC520 microcontroller includes an integrated PCI bus host bridge controller. The

host bridge allows the Am5x86 CPU to generate PCI bus master cycles and allows PCI bus

masters to access the ÉlanSC520 microcontroller’s SDRAM.

The host bridge register set includes three groups of registers:

s Six memory-mapped configuration region (MMCR) registers are used to configure and

control most functions specific to the ÉlanSC520 microcontroller host bridge.

s Two direct-mapped I/O addresses are used to access the PCI bus configuration space

for both the host bridge and for any other devices present on the PCI bus.

s Five host bridge-specific PCI bus indexed registers in the PCI bus configuration space

provide the mandatory header registers that are required for any PCI bus device, plus

the Master Retry Time-Out register.

In addition to the host bridge, the PCI bus can contain several other devices, each with its

own PCI configuration space that is also accessed via the two PCI direct-mapped registers.

Access from other PCI bus masters to the host bridge registers is not supported. The host

bridge implements only those configuration registers that are related to the host bridge

functions.

See the

Élan™SC520 Microcontroller User’s Manual, order #22004, for details about the

host bridge controller.

Table 6-1, Table 6-2 on page 6-2, and Table 6-3 on page 6-2 list each type of host bridge

controller register in offset order with the corresponding description’s page number.

6.2

REGISTERS

Table 6-1

PCI Bus Host Bridge MMCR Registers

Mnemonic

MMCR Offset

Page Number

Host Bridge Control

HBCTL

60h

page 6-3

Host Bridge Target Interrupt Control

HBTGTIRQCTL

62h

page 6-5

Host Bridge Target Interrupt Status

HBTGTIRQSTA

64h

page 6-7

Host Bridge Master Interrupt Control

HBMSTIRQCTL

66h

page 6-9

Host Bridge Master Interrupt Status

HBMSTIRQSTA

68h

page 6-12

Host Bridge Master Interrupt Address

MSTINTADD

6Ch

page 6-14

ELANSC520 Datasheet(PDF) 65 Page - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 65 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL