ELANSC520 datasheet(69/440 Pages) AMD

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PCI Bus Host Bridge Registers

Élan™SC520 Microcontroller Register Set Manual

6-5

Host Bridge Target Interrupt Control (HBTGTIRQCTL)

Memory-Mapped

MMCR Offset 62h

This register contains bit fields for configuring and enabling host bridge target interrupts.

Bit Definitions

Bit

Reserved

T_DLYTO_

IRQ_SEL

T_APER_

IRQ_SEL

T_DPER_

IRQ_SEL

Reset

00000000

R/W

RSV

R/W

Bit

Reserved

T_DLYTO_

IRQ_ENB

T_APER_

IRQ_ENB

T_DPER_

IRQ_ENB

Reset

00000000

R/W

RSV

R/W

Bit

Name

Function

–11

Reserved

This bit field should be written to 0 for normal system operation.

T_DLYTO_

IRQ_SEL

Target Delayed Transaction Time-Out Interrupt Select

This bit allows delayed transaction time-outs to generate an NMI instead of a maskable

interrupt.

0 = Delayed transaction time-outs generate a maskable interrupt.

1 = Delayed transaction time-outs generate an NMI.

T_APER_

IRQ_SEL

Target Address Parity Interrupt Select

This bit allows address parity errors detected by the target controller to generate an NMI

instead of a maskable interrupt.

0 = Address parity errors generate a maskable interrupt.

1 = Address parity errors generate an NMI.

T_DPER_

IRQ_SEL

Target Data Parity Interrupt Select

This bit allows data parity errors detected by the target controller to generate an NMI instead

of a maskable interrupt.

0 = Data parity errors generate a maskable interrupt.

1 = Data parity errors generate an NMI.

–3

Reserved

This bit field should be written to 0 for normal system operation.

2T_DLYTO_

IRQ_ENB

Target Delayed Transaction Time-Out Interrupt Enable

This bit allows delayed transaction time-outs to generate an interrupt.

0 = Delayed transaction time-outs do not generate an interrupt.

1 = Delayed transaction time-outs generate an interrupt.

T_APER_

IRQ_ENB

Target Address Parity Interrupt Enable

This bit allows address parity errors detected by the target controller to generate an interrupt.

0 = Address parity errors do not generate an interrupt.

1 = Address parity errors generate an interrupt.

ELANSC520 Datasheet(PDF) 69 Page - Advanced Micro Devices

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