ELANSC520 datasheet(78/440 Pages) AMD

78 / 440 page

PCI Bus Host Bridge Registers

6-14

Élan™SC520 Microcontroller Register Set Manual

Host Bridge Master Interrupt Address (MSTINTADD)

Memory-Mapped

MMCR Offset 6Ch

This bit field reports the address of the transaction during which the master controller detected an error condition.

Bit Definitions

Programming Notes

This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset

is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3).

Bit

M_AD_IRQ_ID[31

–24]

Reset

00000000

R/W

Bit

M_AD_IRQ_ID[23

–16]

Reset

00000000

R/W

Bit

M_AD_IRQ_ID[15

–8]

Reset

00000000

R/W

Bit

M_AD_IRQ_ID[7

–0]

Reset

00000000

R/W

Bit

Name

Function

–0

M_AD_IRQ_ID

[31

–0]

Master Address Interrupt Identification

This bit field reports the address of the transaction during which the master controller

detected an error condition. If multiple errors are detected, only the address of the first error is

latched. This bit field is only valid when an interrupt status bit is set. It is cleared when any

interrupt status bit is cleared.

A value of 00000000h means the address was not latched (unless the error happened to

occur at address 00000000h). For example, the address is not latched if multiple interrupts

are pending and one interrupt status was cleared.

When multiple interrupts are pending, there is no indication of which interrupt the address

corresponds to.

The M_CMD_IRQ_ID bit field in the HBMSTIRQSTA register (see page 6-12) contains the

command of the transaction during which the master controller detected an error condition.

ELANSC520 Datasheet(PDF) 78 Page - Advanced Micro Devices

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