ELANSC520 datasheet(40/440 Pages) AMD

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System Address Mapping Registers

2-8

Élan™SC520 Microcontroller Register Set Manual

Programming Notes

Each PARx register must be written as a full 32-bit doubleword.

The basic trade-off with setting the page size in a PARx register is the granularity of the memory region. The smaller

page size restricts the total size of the region, but allows the smaller granularity of 4 Kbytes. The larger 64-Kbyte

page size is an option when the total region size must be larger than 512 Kbytes, but this requires the pages to start

on 64-Kbyte boundaries.

If two PARx windows overlap, the lower-numbered PARx register’s target has priority. For example, if a memory or

I/O address falls within the windows defined by both the PAR4 register and the PAR 13 register, reads or writes to

that address go to the PAR4 register’s target, not the one defined in the PAR13 register.

If a PARx window overlaps the MMCR alias defined by the CBAR register (see page 2-9), the MMCR alias has

priority, with the following exception: if a PAR window is configured for PCI,

and the CBAR register is programmed

to overlap with this PAR window,

and the PAR window is placed below the top of DRAM, then the MMCR is not given

priority over the PCI access. This configuration could result in system errors due to concurrence of both PCI and

internal MMCR accesses.

PARx windows in the GP bus I/O space must not include any of the following direct-mapped register addresses:

CBAR (Port FFFCh), PCICFGADR (Port 0CF8h), or PCICFGDATA (Port 0CFCh). Also, the PARx window must not

overlap any direct-mapped I/O address belonging to an internal peripheral (i.e., GP bus DMA, PIC, PIT, system

control ports, RTC, or UART I/O registers).

When programming a PARx register for GP bus I/O space, it is best to start the space on a doubleword boundary.

If an unaligned byte region is specified for I/O access, the software that accesses the region must directly address

the correct byte or bytes. For example, if a PARx register is programmed for an I/O region starting at address xxx1h

(i.e., byte1 of the associated doubleword), then when the CPU performs a word or doubleword access, the entire

access is redirected to the PCI bus, and byte 1 is not accessed on the GP bus as programmed. In this case the byte

requested

must be directly accessed by the CPU at I/O address xxx1h.

–0

SZ_ST_ADR

[24

–0]

Region Size/Start Address

This bit field, in conjunction with the PG_SZ bit, is used to specify the total region size and the

starting address of the programmed address space. This bit field is used in one of three ways:

For Memory Space Regions with 4-Kbyte Pages:

The PG_SZ bit is 0.

The SZ_ST_ADR[24

–18] bit field is used to specify a memory space size of up to 128

pages, each 4 Kbytes in size, for a maximum PARx window size of 512 Kbytes. Pages start

on 4-Kbyte boundaries. (A value of 00h specifies one page; 7Fh specifies 128 pages.)

The SZ_ST_ADR[17

–0] bit field is used to define the starting page of the region within the

memory address space. The SZ_ST_ADR[17

–0] bit field is compared to internal Am5x86

CPU bus signals a29

–a12.

For Memory Space Regions with 64-Kbyte Pages:

The PG_SZ bit is 1.

The SZ_ST_ADR[24

–14] bit field is used to specify a memory space size of up to 2048

pages, each 64 Kbytes in size, for a maximum PARx window size of 128 Mbytes. Pages

start on 64-Kbyte boundaries. (A value of 000h specifies one page; 7FFh specifies 2048

pages.)

The S Z_ST_ADR[13

–0] bit field is used to define the starting page of the region within the

memory address space. The SZ_ST_ADR[13

–0] bit field is compared to internal Am5x86

CPU bus signals a29

–a16.

For I/O Space Regions:

The PG_SZ bit is ignored.

The SZ_ST_ADR[24

–16] bit field is used to specify an I/O space size of byte granularity,

for a total size up to 512 bytes. (A value of 000h specifies one byte; 1FFh specifies 512 bytes.)

The SZ_ST_ADR[15

–0] bit field is used to define the starting address of the window within

the 64 -Kbyte I/O space. The SZ_ST_ADR[15

–0] bit field is compared to internal Am5x86

CPU bus signals a15

–a0.

Note: If a larger window than the maximum size is required, multiple PARx registers can be

used.

Bit

Name

Function

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