ELANSC520 datasheet(62/440 Pages) AMD

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System Arbitration Registers

5-6

Élan™SC520 Microcontroller Register Set Manual

Arbiter Priority Control (ARBPRICTL)

Memory-Mapped

MMCR Offset 74h

This register defines priorities for the PCI bus arbiter.

Bit Definitions

Bit

CPU_PRI[1–0]

Reserved

Reset

01000000

R/W

RSV

Bit

Reserved

Reset

00000000

R/W

RSV

Bit

Reserved

HI_PRI_1_SEL[3–0]

Reset

00001111

R/W

RSV

R/W

Bit

Reserved

HI_PRI_0_SEL[3–0]

Reset

00001111

R/W

RSV

R/W

Bit

Name

Function

31–30

CPU_PRI[1–0]

PCI Bus Arbiter CPU Priority

This bit field defines the relative Am5x86 CPU PCI master priority.

00 = Reserved.

01 = The Am5x86 CPU is granted the PCI Bus after every one external PCI master cycle.

10 = The Am5x86 CPU is granted the PCI Bus after every two external PCI master cycles.

11 = The Am5x86 CPU is granted the PCI Bus after every three external PCI master cycles.

29–12

Reserved

This bit field should be written to 0 for normal system operation.

ELANSC520 Datasheet(PDF) 62 Page - Advanced Micro Devices

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