ELANSC520 datasheet(48/440 Pages) AMD

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Reset Generation Registers

3-6

Élan™SC520 Microcontroller Register Set Manual

Programming Notes

Unlike most other registers, the bits in this register are only returned to their reset value by a PWRGOOD reset. They

are not cleared by any other kind of reset.

The AMDebug technology trace information is preserved only if a soft reset is generated to the CPU.

See the

Élan™SC520 Microcontroller User’s Manual, order #22004, for details about reset generation. Table 3-3

provides a summary of ÉlanSC520 microcontroller reset sources and effects.

SD_RST_DET

CPU Shutdown Reset Detect

This bit is set when a CPU shutdown cycle (typically caused by a software “triple-fault”) is

detected. Software clears this bit by writing a 1.

0 = No CPU shutdown cycle was detected.

1 = The CPU soft reset event was from a shutdown cycle.

A soft reset event clears the NMI_ENB bit in the PICICR register (see page 12-4). This allows

software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset.

PRGRST_DET

PRGRESET Detect

This bit is set when a reset from PRGRESET pin is detected. Software clears this bit by

writing a 1.

0 = No PRGRESET pin reset was detected.

1 = The system reset event was from the PRGRESET pin.

If the PRG_RST_ENB bit is 1 in the RESCFG register (see page 3-3), assertion of the

PRGRESET pin while PWRGOOD is asserted results in a programmable reset in which the

SDRAM configuration is maintained.

PWRGOOD_

DET

POWERGOOD Reset Detect

This bit is set when a reset from the PWRGOOD pin is detected. Software clears this bit by

writing a 1.

0 = No PWRGOOD pin reset was detected.

1 = The system reset event was from the PWRGOOD pin.

This reset event has higher priority over PRGRESET and disables the PRGRESET function (if

it is enabled) by clearing the PRG_RST_ENB bit in the RESCFG register (see page 3-3).

Table 3-3

Microcontroller Reset Sources

Source

CPU

(Hard/Soft)

GPRESET

RST Pin

(PCI)

Internal

Registers

Notes

PWRGOOD pin

Hard

PRGRESET pin

Hard

1,2

Notes:

1. The PRG_RST_ENB bit must be set in the RESCFG register (see page 3-3) to enable the reset function on this pin.

2. If the PRG_RST_ENB bit is set, the SDRAM controller configuration is maintained to support system reset in which SDRAM

contents are also maintained.

SYS_RST bit, RESCFG register (see page 3-4)

Hard

Watchdog timer reset event (page 16-2)

Hard

AMDebug technology system reset

Hard

CPU_RST bit, SYSCTLA register (page 3-9)

Soft

3. Any write of a 1 to the CPU_RST bit causes a soft reset, regardless of whether the bit was previously 1 or 0.

SCP soft reset, SCPCMD register (page 3-7)

Soft

CPU shutdown (typically caused by a triple-fault)

Soft

GP_RST bit, RESCFG register (page 3-3)

PCI_RST bit, HBCTL register (page 6-3)

Bit

Name

Function

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