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ELANSC520 Datasheet(PDF) 26 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 26 Page - Advanced Micro Devices

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Configuration Register Overview
1-6
Élan™SC520 Microcontroller Register Set Manual
Floating Point Error Interrupt Mapping
FERRMAP
D46h
page 12-21
GPIRQ0 Interrupt Mapping
GP0IMAP
D50h
page 12-21
GPIRQ1 Interrupt Mapping
GP1IMAP
D51h
page 12-21
GPIRQ2 Interrupt Mapping
GP2IMAP
D52h
page 12-21
GPIRQ3 Interrupt Mapping
GP3IMAP
D53h
page 12-21
GPIRQ4 Interrupt Mapping
GP4IMAP
D54h
page 12-21
GPIRQ5 Interrupt Mapping
GP5IMAP
D55h
page 12-21
GPIRQ6 Interrupt Mapping
GP6IMAP
D56h
page 12-21
GPIRQ7 Interrupt Mapping
GP7IMAP
D57h
page 12-21
GPIRQ8 Interrupt Mapping
GP8IMAP
D58h
page 12-21
GPIRQ9 Interrupt Mapping
GP9IMAP
D59h
page 12-21
GPIRQ10 Interrupt Mapping
GP10IMAP
D5Ah
page 12-21
Reset Generation
D70–D74h
System Board Information
SYSINFO
D70h
page 3-2
Reset Configuration
RESCFG
D72h
page 3-3
Reset Status
RESSTA
D74h
page 3-5
GP DMA Controller
D80–DBEh
GP-DMA Control
GPDMACTL
D80h
page 11-4
GP-DMA Memory-Mapped I/O
GPDMAMMIO
D81h
page 11-5
GP-DMA Resource Channel Map A
GPDMAEXTCHMAPA
D82h
page 11-6
GP-DMA Resource Channel Map B
GPDMAEXTCHMAPB
D84h
page 11-8
GP-DMA Channel 0 Extended Page
GPDMAEXTPG0
D86h
page 11-10
GP-DMA Channel 1 Extended Page
GPDMAEXTPG1
D87h
page 11-11
GP-DMA Channel 2 Extended Page
GPDMAEXTPG2
D88h
page 11-12
GP-DMA Channel 3 Extended Page
GPDMAEXTPG3
D89h
page 11-13
GP-DMA Channel 5 Extended Page
GPDMAEXTPG5
D8Ah
page 11-14
GP-DMA Channel 6 Extended Page
GPDMAEXTPG6
D8Bh
page 11-15
GP-DMA Channel 7 Extended Page
GPDMAEXTPG7
D8Ch
page 11-16
GP-DMA Channel 3 Extended Transfer Count
GPDMAEXTTC3
D90h
page 11-17
GP-DMA Channel 5 Extended Transfer Count
GPDMAEXTTC5
D91h
page 11-18
GP-DMA Channel 6 Extended Transfer Count
GPDMAEXTTC6
D92h
page 11-19
GP-DMA Channel 7 Extended Transfer Count
GPDMAEXTTC7
D93h
page 11-20
Buffer Chaining Control
GPDMABCCTL
D98h
page 11-21
Buffer Chaining Status
GPDMABCSTA
D99h
page 11-22
Buffer Chaining Interrupt Enable
GPDMABSINTENB
D9Ah
page 11-24
Buffer Chaining Valid
GPDMABCVAL
D9Bh
page 11-25
GP-DMA Channel 3 Next Address Low
GPDMANXTADDL3
DA0h
page 11-26
GP-DMA Channel 3 Next Address High
GPDMANXTADDH3
DA2h
page 11-27
GP-DMA Channel 5 Next Address Low
GPDMANXTADDL5
DA4h
page 11-28
GP-DMA Channel 5 Next Address High
GPDMANXTADDH5
DA6h
page 11-29
GP-DMA Channel 6 Next Address Low
GPDMANXTADDL6
DA8h
page 11-30
Table 1-1
Memory-Mapped Configuration Region (MMCR) Registers (By Offset) (Continued)
Register Name
Mnemonic
MMCR Offset Page Number



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