ELANSC520 datasheet(72/440 Pages) AMD

72 / 440 page

PCI Bus Host Bridge Registers

6-8

Élan™SC520 Microcontroller Register Set Manual

Programming Notes

This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset

is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3).

T_APER_

IRQ_STA

Target Address Parity Interrupt Status

This bit is set when the target controller detects an address parity error.

0 = Address parity error has not occurred.

1 = Address parity error has occurred.

This bit is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (T_APER_IRQ_ENB in

the HBTGTIRQCTL register, see page 6-5), or the Parity Error Response bit (PERR_RES in

the PCISTACMD register, see page 6-21).

T_DPER_

IRQ_STA

Target Data Parity Interrupt Status

This bit is set when the target controller detects a data parity error.

0 = Data parity error has not occurred.

1 = Data parity error has occurred.

This bit is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (T_DPER_IRQ_ENB in

the HBTGTIRQCTL register, see page 6-6), or the Parity Error Response bit (PERR_RES in

the PCISTACMD register, see page 6-21).

Bit

Name

Function

ELANSC520 Datasheet(PDF) 72 Page - Advanced Micro Devices