ELANSC520 datasheet(81/440 Pages) AMD

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PCI Bus Host Bridge Registers

Élan™SC520 Microcontroller Register Set Manual

6-17

PCI Configuration Data (PCICFGDATA)

Direct-Mapped

I/O Address 0CFCh

Software reads or writes this register to initiate a PCI bus configuration cycle after setting up the PCICFGADR register

(see page 6-15).

Bit Definitions

Programming Notes

The ENABLE bit must be set in the PCICFGADR register for an access to this register (PCICFGDATA) to result in

a PCI bus configuration cycle. Otherwise the cycle accesses the PCI bus I/O space.

This register can be accessed as a doubleword, word, or byte. The appropriate CBEx signal combinations are driven

on the PCI bus during the data phase of the configuration cycle.

In the ÉlanSC520 microcontroller, the doubleword starting at 0CFCh must not be mapped to the GP bus.

Bit

CFG_DATA[31–24]

Reset

xxxxxxxx

R/W

Bit

CFG_DATA[23–16]

Reset

xxxxxxxx

R/W

Bit

CFG_DATA[15–8]

Reset

xxxxxxxx

R/W

Bit

CFG_DATA[7–0]

Reset

xxxxxxxx

R/W

Bit

Name

Function

31–0

CFG_DATA

[31–0]

Configuration Data

This bit field contains the data for the configuration access cycle (read or write).

ELANSC520 Datasheet(PDF) 81 Page - Advanced Micro Devices

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