ELANSC520 datasheet(89/440 Pages) AMD

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Élan™SC520 Microcontroller Register Set Manual

7-1

CHAPTER

7 SDRAM CONTROLLER REGISTERS

7.1

OVERVIEW

This chapter describes the synchronous dynamic random-access memory (SDRAM)

controller registers of the ÉlanSC520 microcontroller.

The ÉlanSC520 microcontroller includes an integrated SDRAM controller. The following

are some of the SDRAM controller’s main features:

s Synchronous DRAM support

s Support for up to 4 banks

s Up to 256 Megabytes of SDRAM

s ECC (single-bit correction/multiple-bit detection) support

The SDRAM controller register set consists of ten memory-mapped configuration region

(MMCR) registers used for configuration, control, and status. See the

Élan™SC520

Microcontroller User’s Manual, order #22004, for details about using the SDRAM controller.

Table 7-1 lists the SDRAM controller registers in offset order, with the corresponding

description’s page number.

7.2

REGISTERS

Table 7-1

SDRAM Controller MMCR Registers

Mnemonic

MMCR Offset

Page

Number

SDRAM Control

DRCCTL

10h

page 7-2

SDRAM Timing Control

DRCTMCTL

12h

page 7-4

SDRAM Bank Configuration

DRCCFG

14h

page 7-5

SDRAM Bank 0–3 Ending Address

DRCBENDADR

18h

page 7-7

ECC Control

ECCCTL

20h

page 7-9

ECC Status

ECCSTA

21h

page 7-10

ECC Check Bit Position

ECCCKBPOS

22h

page 7-11

ECC Check Code Test

ECCCKTEST

23h

page 7-12

ECC Single-Bit Error Address

ECCSBADD

24h

page 7-14

ECC Multi-Bit Error Address

ECCMBADD

28h

page 7-15

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